MC100EL29 |
RFQ for MC100EL29 Required Field |
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| Technical/Catalog Information | MC100EL29DW |
| Vendor | ON Semiconductor |
| Category | Integrated Circuits (ICs) |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (7.5mm Width) |
| Function | Set and Reset |
| Number of Bits per Element | 1 |
| Number of Elements | 2 - Dual |
| Current - Output High, Low | - |
| Output Type | Differential |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Packaging | Tube |
| Operating Temperature | -40°C ~ 85°C |
| Delay Time - Propagation | 500ps |
| Frequency - Clock | - |
| Voltage - Supply | 4.2 V ~ 5.7 V |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | MC100EL29DW MC100EL29DW MC100EL29DWOS ND MC100EL29DWOSND MC100EL29DWOS |
| Product | Manufacturers | Pack | D/C |
| MC100EL29 | - | - | - |
The MC100LVEL29 is a dual masterslave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100EL29 is pin and functionally equivalent to the MC100LVEL29 but is specified for operation at the standard 100E ECL voltage supply. A VBB output is provided for AC coupling, refer to the interfacing section of the
ECLinPS Data Book (DL140) for more information on AC coupling ECL signals. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE and the D input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.
Features |
| ` 1100MHz FlipFlop Toggle Frequency` 20lead SOIC Package` 580ps Propagation Delays |
